The present invention relates generally to a transistor circuit. More specifically, the invention relates to a transistor circuit employing peripheral driver circuits, such as a liquid crystal display, a contact type image sensor, a liquid crystal shutter, a vacuum fluorescent display and so forth.
In the peripheral drivers, such liquid crystal display, contact type image sensor, liquid crystal shutter, vacuum fluorescent display and so forth, a technology for integrally fabricating the peripheral driver circuit and the display element thereof in order for reduction of size and cost and for attaining high reliability, has been widely employed. By fabricating the pixel electrode as electrode of the display element and the peripheral driver circuit on a common substrate, it becomes possible to significantly reduce number of terminals for mutual connection and number of external driver IC chips. Furthermore, it becomes possible to solve a problem in reliability which is limited due to limit of precision in a bonding process for large area and high density IC chips.
The peripheral driver circuit for these display elements, particularly for liquid crystal display element, normally includes shift register circuits, output buffer circuits and switches. Furthermore, in the shift register circuit, inverter circuits and switches are included. The output buffer circuit is formed by connecting inverter circuits in a cascade configration. The inverter circuit employed in such shift register circuit and the output buffer circuit is a basic component of the peripheral driver circuit.
Referring to FIG. 8, the conventional inverter circuit illustrated therein has an input terminal 100, an output terminal 200, a P-channel type gate insulated field effect transistor (P-type MOS transistor) 1 and N-channel type gate insulated field effect transistor (N-type MOS transistor) 2. The drain electrode of the P-type MOS transistor 1 which is connected to a power supply voltage Vdd at the source electrode, is commonly connected to the output terminal 200 and the drain electrode of the N-type MOS transistor 2. The source electrode of the N-type MOS transistor 2 is connected to a ground potential. Respective gate electrodes are commonly connected to the input terminal 100. As these MOS transistors, polycrystalline silicon thin film transistor (p-Si FET) is employed.
Again reference is made to FIG. 8, P-type MOS transistor 1 is designed such that an ON current flows from the source electrode to the drain electrode when the voltage supplied to the gate electrode becomes lower than Vdd-.vertline.Vtp.vertline. (Vtp: an absolute value of a threshold voltage of the P-type MOS transistor). N-type MOS transistor 2 is designed to initiate flow of ON current when the potential at the gate electrode becomes higher than the threshold voltage thereof. Accordingly, when the input signal is high (H), the transistor 1 becomes OFF state, the transistor 2 becomes ON state to supply low (L) level to the output terminal 200. On the other hand, when the input signal is low (L) level, the transistor 1 becomes ON state and the transistor 2 becomes OFF state to supply H level to the output terminal 200.
In the above-mentioned peripheral driver circuit integrated liquid crystal display, N-type MOS transistor for a switching element is arranged for each pixel. To the drain electrode of the N-type MOS transistor for switching element, an image signal line is connected to apply a 12 volt data signal. The data signal has to be transferred to a pixel electrode arranged at the side of the source electrode. Therefore, typically, a gate pulse having a pulse amplitude of approximately 20 volts (12 volts+threshold voltage Vth of the N-type MOS transistor) is supplied to the gate electrode of the N-type MOS transistor. Namely, the peripheral driver circuit has to be driven by the power supply voltage of 20 volts.
Referring to FIG. 9, there are illustrated input and output waveforms when the conventional inverter circuit is driven by the power supply voltage of 20 volts, and source-drain voltage waveforms of the transistor 1 and the transistor 2. When the input voltage Vin is 20 volts, and thus the output voltage Vout is 0 volt, the source-drain voltage Vds1 of the transistor 1 is 20 volts as the transistor 1 is in OFF state and the source-drain voltage Vds2 of the transistors 2 is 0 volt as the transistor 2 is in ON state.
On the other hand, when the input voltage is 0 volt and thus the output voltage Vout is 20 volts, the source-drain voltage Vds2 is 20 volts. Accordingly, in order to attain stable operation of the peripheral driver circuit, the source-drain breakdown voltage is necessary higher than 20 volts.
On the other hand, associating with shortening channel length of the transistor, a generation of a hot carrier should creates a problem of degradation of the characteristics. The hot carrier degradation is substantial in the case of N-type MOS transistor. The hot carrier is caused by acceleration of the electron flowing from the source electrode to the drain electrode by a high electricfield at the edge of the drain electrode. The electron injected within a high field region in the vicinity of the drain electrode generates a large number of electron and hole through impact ionization. These hot carriers turn excessive drain current or are injected to the oxide layer. As a result, degradation of the source-drain breakdown voltage, increasing of the threshold voltage, lowering of a transconductance are caused.
In general, the hot carrier becomes a problem when a channel length is less than or equal to 2 .mu.m in an IC chip of a monocrystalline silicon which is driven at 5 volt. However, as set forth above, in the peripheral driver circuit for the liquid crystal display, it is required to drive at 20 volts. Therefore, even in a channel length range (e.g. 4 .mu.m) at which the hot carrier will not raise the problem at 5 volts, a hot carrier degradation will be caused.
As a solution for this, it is most effective to employ a structure for lowering field strength of the drain electrode, such as an offset gate structure or LDD (Lightly Doped Drain) structure. However, in case of the offset gate structure, it is not always an ideal structure in view of operation speed of the driver circuit for low ON current. On the other hand, in case of the LDD structure, process steps are increased to lower yield to cause rising of a cost.
On the other hand, in the peripheral driver circuit for the liquid crystal display, the contact-type image sensor or so forth, one of the most important circuit is a scanning circuit. The scanning circuit typically comprises a shift register and an output buffer circuit. In the recent years, a level shifter circuit for converting the output voltage level is often used as an interface circuit between shift register circuit and the output buffer circuit.
This is intended achieve low power consumption and high reliability by operating the shift register at high speed by a lower voltage than the driving voltage of the output buffer. Toward the future, the level shifter circuit will perform more important functions.
FIG. 10 is a circuit diagram showing a circuit including the conventional level shifter circuit and its peripheral circuit. The shown level shifter circuit is provided between the shift register circuit 20 and the output buffer circuit 30. The level shifter circuit comprises a level shifter portion 11 and an inverter portion 12.
The shift register circuit 20 is operated with a low power supply voltage Vdd2 and the maximum output voltage is Vdd2. The level shifter portion 11 operates with high power supply voltage Vdd1 and the maximum output voltage Vout is Vdd1.
In the level shifter portion 11, the input signal Vin supplied from the shift register circuit 20 is supplied to the gate electrode of the N-type MOS transistor 2. The drain output Va of the MOS transistor 2 is supplied to the gate electrode of the P-type MOS transistor 5. On the other hand, an inverted signal of the input signal Vin inverted by the inverter portion 12 is applied to the gate electrode of the N-type MOS transistor 6. The drain output of the N-type MOS transistor 6 becomes the circuit output Vout, and, as well, is applied to the gate electrode of the P-type MOS transistor 1.
The P-type MOS transistor 1 and the N-type MOS transistor 2 are connected in cascade configration between the supply voltage Vdd1 and the ground potential. Also, the P-type MOS transistor 5 and the N-type MOS transistor 6 are connected in cascade configration between the power supply voltage Vdd1 and the ground potential.
The inverter portion 12 operates with a power supply voltage Vdd2 and is a known circuit construction of cascade connection of a P-type MOS transistor 9 and a N-type MOS transistor 10. By this inverter portion 12, the input signal Vin is inverted to be the gate input for the transistor 6.
It should be noted that such construction of the level shifter circuit has been disclosed in Japanese Unexamined Patent Publications Nos. 62-269419 and 63-105522.
In this example, the power supply voltage Vdd2 for the shift register circuit 20 and the inverter portion 12 is set at substantially half of the power supply voltage Vdd1 for the level shifter portion 11. Accordingly, the maximum voltage levels of the input signal Vin and its inverted signal become half of Vdd1. FIG. 11 shows voltage waveforms at respective portion of the level shifter portion 11. When the input signal Vin is low level (0 V), the transistor 2 becomes OFF and the transistor 6 becomes ON. Therefore, the potential at the gate electrode of the transistor 1 falls to the ground potential to turn the transistor 1 ON. By turning ON of the transistor 1, the power supply voltage Vdd1 is supplied to the gate electrode of the transistor 5 to turn the latter OFF. As a result of this, the output signal Vout becomes 0 V of the low level.
On the other hand, when the input signal Vin becomes high level, the transistors 2, 5 become ON and the transistors 6, 1 become OFF. Thus, the output signal Vout becomes high level, i.e. Vdd1. Thus, the input signal Vin of the maximum voltage Vdd2 is converted into the output signal Vout of the maximum voltage Vdd1.
For instance, in case of the liquid crystal display, a video signal Vv having an amplitude of 12 V is transmitted to the source electrode of a MOS transistor 41 for each pixel of a liquid crystal display portion 40 composed of a liquid crystal cell 42 and N-type MOS transistor 41. In order to efficiently transmit this video signal Vv to the liquid crystal cell 42, the gate voltage of the transistor 41 is set at approximately 20 V which is higher than the video signal Vv in the extent of the threshold voltage of the transistor 41.
Namely, the voltage for driving the gate electrode of the transistor 41 for the liquid crystal display portion 40 in response to the output signal Vout of the level shifter portion 11, namely the maximum voltage of the output signal Vout of the level shifter portion 11 is set at approximately 20 V. Therefore, the power source voltage Vdd1 is also set at approximately 20 V.
Here, when the input signal Vin is a low level, the source-drain voltage Vds2 of the transistor 2 becomes substantially equal to the power supply voltage Vdd1. On the other hand, when the input signal Vin is a high level, the source-drain voltage Vds6 of the MOS transistor 6 becomes substantially equal to the power supply voltage Vdd1. Therefore, it becomes necessary to set the source-drain breakdown voltages of the transistors 2 and 6 higher than the power source voltage Vdd1 (20 V).
Accordingly, even with this level shifter circuit, the similar problem that is arisen by the inverter circuit of FIG. 8 is inherently caused.